IBM breaks nanometer barrier with next-generation chip technology

IBM has achieved a significant milestone in semiconductor technology, presenting the world's first sub-1-nanometer chip. This groundbreaking development, based on a novel 0.7-nanometer (7 angstroms) transistor architecture, is poised to extend the evolution of processors for the next decade.

The industry has long grappled with the physical limitations of shrinking transistors. However, IBM's 'nanostack' technology introduces a new approach. Instead of a flat surface, this 3D architecture stacks transistors vertically, dramatically increasing processing capacity and energy efficiency. A chip the size of a fingernail can now house nearly 100 billion transistors, doubling the density achieved with IBM's 2-nanometer technology introduced in 2021.

Early results suggest this innovation could yield substantial improvements, offering up to 50% more performance or a 70% boost in energy efficiency. These enhancements are critical for meeting the escalating demands of artificial intelligence, cloud services, and next-generation electronic devices. The ability to optimize performance and energy consumption independently by using different materials in each layer of the chip further enhances its potential.

Jay Gambetta, director of IBM Research and IBM Fellow, stated that this advancement marks a "decisive moment for computing," moving beyond the nanometer era towards atomic-scale technology. He emphasized that the nanostack architecture not only creates smaller transistors but fundamentally re-imagines chip construction for greater power and efficiency. Additionally, the technology has achieved a 40% reduction in SRAM (Static Random-Access Memory) scale, the most significant leap in approximately a decade for this component, which is vital for AI applications requiring rapid memory access.

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The most recent advance by IBM marks a decisive moment for computing by taking technology beyond the nanometer era, towards a scale close to that of atoms. With our new nanostack architecture, we are not only manufacturing smaller transistors but reinventing the way chips are built to offer much greater power and energy efficiency.