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TSMC's HBM packaging challenges create opportunity for Intel, report says

From Liberty Times · () Chinese

Translated from Chinese and summarized by DistantNews. Read the original for the full story.

At a glance

News Named sources Context piece
  • Intel is reportedly finding new opportunities in the AI chip market due to challenges faced by TSMC in packaging High Bandwidth Memory (HBM) with AI accelerators.
  • TSMC's CoWoS packaging technology is reportedly experiencing yield risks, capacity constraints, and high scrap costs, potentially benefiting Intel's EMIB packaging solution.
  • While TSMC's overall yield remains strong, capacity shortages and the pursuit of alternative suppliers by AI clients present a chance for Intel to regain ground in advanced packaging.

Intel may be poised to gain an advantage in the competitive AI chip landscape, as reports suggest that Taiwan Semiconductor Manufacturing Co. (TSMC) is encountering significant hurdles in its advanced packaging processes for High Bandwidth Memory (HBM) integrated with AI accelerators.

According to industry analysis, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, a mainstream solution for major AI clients like Nvidia and AMD, is reportedly facing challenges related to yield rates, production capacity, and high scrap costs. Integrating HBM with AI chips requires large silicon interposers, which increases costs and complexity, and any issues in the final packaging stages can lead to the loss of expensive GPUs and multiple HBM stacks.

TSMC's CoWoS has long been the mainstream packaging solution for AI customers such as Nvidia, AMD, and Broadcom, but HBM must be integrated with AI chips through large silicon interposers, which is not only costly and thick but also carries risks of yield and high scrap costs.

— Neil ShahNeil Shah, co-founder of Counterpoint Research, explains the challenges associated with TSMC's CoWoS packaging for HBM integration.

This situation presents a potential opening for Intel, whose EMIB (Embedded Multi-Die Interconnect Bridge) technology offers a different approach. Unlike CoWoS, EMIB embeds localized silicon bridges within an organic substrate, enabling direct, high-speed interconnects between chiplets. Intel has already been applying this technology to products like Sapphire Rapids and Ponte Vecchio and is expanding its advanced packaging capacity in New Mexico.

While analysts suggest that TSMC's existing CoWoS yield rates are still generally excellent and that recent issues might be isolated to new versions like CoWoS-L, the persistent capacity crunch is undeniable. As AI customers begin to seek second-sourcing options, Intel's advanced packaging technologies, including EMIB, Foveros, and future solutions like ZAM and XBM, could become a crucial factor in its strategy to re-establish a strong presence in the AI supply chain.

The real pressure is still insufficient capacity.

— Mike DemlerAnalyst Mike Demler comments on the primary challenge facing TSMC's packaging solutions.
About this summary

Originally published by Liberty Times in Chinese. Translated, summarized, and contextualized automatically by DistantNews, with a note on how the source frames the story. Not individually reviewed before publishing. How this works.

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