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XCENA to present CXL-based 'MX1' tech at Hot Chips 2026, partners with Samsung
๐Ÿ‡ฐ๐Ÿ‡ท South Korea /Technology

XCENA to present CXL-based 'MX1' tech at Hot Chips 2026, partners with Samsung

From Dong-A Ilbo · () Korean

Translated from Korean, summarized and contextualized by DistantNews.

At a glance

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  • South Korean fabless company XCENA will present its CXL-based 'MX1' technology at the Hot Chips 2026 conference, marking a first for Korean fabless firms in the memory session.
  • XCENA is collaborating with Samsung Electronics on CXL-based memory ecosystem development, jointly presenting the 'XCENA MX1 CXL Computational Memory Device'.
  • The MX1 features a system architecture with 3072 memory computation units (MU) and a memory architecture with hierarchical cache and address translation functions for efficient data processing.

XCENA, a South Korean fabless semiconductor company, is set to make history at the prestigious Hot Chips 2026 conference by becoming the first Korean fabless firm to present in the memory session. This marks a significant milestone for the nation's AI semiconductor industry, following earlier breakthroughs by companies like Rebellions and FuriosaAI at the same event.

The company will showcase its innovative CXL-based 'MX1' computational memory device. XCENA is collaborating closely with Samsung Electronics in developing the CXL-based memory ecosystem, and together they will present key findings on the MX1's hardware architecture, programming model, and performance data. This partnership highlights the growing synergy between Korean tech giants and emerging players in advanced memory technologies.

The MX1 architecture is designed for efficient data processing. It incorporates 3072 memory computation units (MU) organized into subsystems, clusters, and individual units. This design aims to reduce data transfer bottlenecks through a custom-designed Network-on-Chip (NoC). The memory architecture features a hierarchical structure of caches and address translation functions, enabling direct processing of large-scale memory access and parallel tasks within the MX1 itself.

This approach contrasts with traditional CPUs and GPUs. While CPUs focus on general-purpose processing and single-thread performance with fewer cores and large caches, and GPUs handle massive parallel arithmetic operations, the MX1 prioritizes memory bandwidth-centric tasks. By placing thousands of RISC-V-based MUs close to memory, it efficiently handles operations like RAG vector search and in-memory analytics, reducing the need for constant data movement and lowering power consumption per core.

DistantNews Editorial

Originally published by Dong-A Ilbo in Korean. Translated, summarized, and contextualized by our editorial team with added local perspective. Read our editorial standards.