Intel's Advanced Packaging Yield Nears 90%, Costs 50% Less Than TSMC, But Substrate Bottleneck Persists

Intel is reportedly making significant strides with its advanced packaging technology, EMIB-T, potentially challenging Taiwan Semiconductor Manufacturing Company's (TSMC) dominance in the sector. Leaks suggest that Intel's EMIB-T packaging is achieving a yield rate close to 90%, a figure that, if accurate, would be highly competitive.

Furthermore, the cost associated with Intel's EMIB-T packaging is claimed to be approximately 50% lower than TSMC's widely used CoWoS (Chip-on-Wafer-on-Substrate) technology. This cost advantage, combined with high yield rates, could make Intel's offering particularly attractive to chip manufacturers looking to reduce production expenses.

However, a major obstacle to the widespread adoption of EMIB-T is the current yield rate of the associated substrates, which reportedly stands at around 50%. This low substrate yield is identified as the primary bottleneck preventing Intel from scaling up production of its advanced packaging solution.

Industry observers note that Intel is aggressively pursuing its semiconductor manufacturing goals, including the ambitious plan to have its new wafer fab in Ohio operational by 2031, with substantial bonuses offered to meet this target. The progress in EMIB-T packaging is seen as a key component of this broader strategy to regain market share and technological leadership.