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TSMC Executive: Energy Efficiency, Not Just Computing Power, is Key Metric for Customers

From Liberty Times · () Chinese

Translated from Chinese, summarized and contextualized by DistantNews.

At a glance

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  • TSMC's Vice President of Business Development, Kevin Zhang, stated that energy efficiency, not just computing power, is now the core focus for chip development.
  • The company projects significant reductions in chip power consumption and increases in performance by 2028 through advanced processes.
  • This shift reflects the growing concern over the substantial electricity demands of AI models and data centers.

The semiconductor industry is shifting its focus from solely increasing computing power to prioritizing energy efficiency in chip design, according to Kevin Zhang, TSMC's Vice President of Business Development. Zhang explained that the massive electricity consumption driven by artificial intelligence is forcing a reevaluation of chip development strategies.

Customers now care most about 'this indicator' in terms of improving performance without increasing power consumption.

— Kevin ZhangTSMC Vice President of Business Development, highlighting the shift in customer priorities.

Zhang highlighted that customers across various sectors, from smartphones and IoT devices to AI data centers, are now most concerned with enhancing performance without increasing power draw. This emphasis on energy efficiency is becoming the key limiting factor in chip development, moving beyond the traditional pursuit of smaller process nodes.

The energy efficiency of chips is becoming the core of the chip war.

— Kevin ZhangStating the new primary focus in semiconductor development.

TSMC anticipates that by 2028, its chip power consumption could decrease by up to 30% while performance increases by over 20% from its current N2 process to the planned A14 process. This indicates a strategic move towards "system-level energy efficiency optimization" as a new path forward, diverging from the sole reliance on shrinking transistor sizes that characterized Moore's Law.

From N2 process to A14 process, chip power consumption can be reduced by 30%, and performance can be increased by more than 20%.

— Kevin ZhangProjecting future improvements in chip efficiency and performance.

This strategic pivot is also reflected in TSMC's decision to delay the adoption of ASML's next-generation high-numerical-aperture extreme ultraviolet lithography machines. The company's focus on energy efficiency is seen as paramount in the current AI era. Zhang also commented on emerging theories like China's "Tau Scaling Law," suggesting that while novel in presentation, the underlying principles often involve tighter component integration, such as 3D stacking, to improve efficiency, rather than representing a revolutionary innovation.

Huawei's Tau scaling law is not revolutionary innovation; energy efficiency is the core of the chip war.

— Kevin ZhangCommenting on emerging theories and reaffirming TSMC's focus.
DistantNews Editorial

Originally published by Liberty Times in Chinese. Translated, summarized, and contextualized by our editorial team with added local perspective. Read our editorial standards.

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