Powerchip Enters AI Advanced Packaging with Singapore Fab's Silicon Interposer Production

Powerchip Semiconductor Manufacturing (PSMC) is making a significant strategic pivot with its new joint venture 12-inch fab in Singapore (VSMC). The company has struck a deal with a key customer to produce silicon interposers, a critical component for advanced packaging technologies like CoWoS, essential for high-performance AI chips. This move effectively integrates PSMC into the cutting-edge AI supply chain, a sector dominated by giants like TSMC.

This new direction comes with adjustments to the project's financial and operational scope. The total investment has been scaled back from $7.8 billion to $6.7 billion, and the projected maximum monthly wafer capacity has been revised downwards from 55,000 to 44,000 wafers. While these adjustments might seem like a reduction, they represent a calculated move to optimize the product portfolio and enhance profitability by focusing on higher-value, more complex manufacturing processes.

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The 12-inch new fab's capital expenditure has been lowered, but the schedule is progressing on time.

Crucially, PSMC will leverage technology licensing from TSMC for its 130nm to 40nm processes, covering interposers, mixed-signal, and power management applications. The revised investment structure sees PSMC contributing $2.4 billion for a 60% stake, with NXP investing $1.6 billion for 40%, and the remaining capital secured through customer deposits, loans, and government subsidies. Construction is slated to begin in the second half of 2024, with mass production targeted for the first quarter of 2027. This strategic alignment with advanced packaging demands signals PSMC's ambition to carve out a significant niche in the rapidly evolving semiconductor landscape.

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Silicon interposers are core components of 2.5D/3D advanced packaging technology.